For an integrated circuit application that has a high-voltage (e.g., 3.3 V) input signal, a high-voltage device is used to deal with the high-voltage input signal. However, for some integrated circuit designs using certain processes, e.g., a 40 nm process, only low-voltage (e.g., 1.8 V) devices are available. If the low-voltage device is used as the input device of a high-voltage application, it will be over-stressed and cause potential unreliability due to the high-voltage input. For example, a voltage VGS across the gate and the source of a low-voltage transistor or a voltage VGD across the gate and the source of the low-voltage transistor is not expected to be over a certain voltage value, e.g., 1.8V. If the VGS or VGD is subject to a voltage over that value, the transistor is over-stressed.
A conventional way to avoid the above over-stress is using a resistor ladder (series resistors) to scale down the input signal from a high-voltage level to a low-voltage level. However, the resistor ladder functions as a current sink and impacts (e.g., lowers) the input impedance for serial link receiver application, e.g., USB1.1.
Accordingly, new mechanisms are desired to solve the above problem.